NXP Semiconductors /MIMXRT1052 /IOMUXC_GPR /GPR3

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Interpret as GPR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0OCRAM_CTL 0 (DCP_KEY_SEL_0)DCP_KEY_SEL 0 (OCRAM_STATUS_0)OCRAM_STATUS

DCP_KEY_SEL=DCP_KEY_SEL_0, OCRAM_STATUS=OCRAM_STATUS_0

Description

GPR3 General Purpose Register

Fields

OCRAM_CTL

OCRAM_CTL[3] - write address pipeline control bit

DCP_KEY_SEL

Select 128-bit dcp key from 256-bit key from snvs/ocotp

0 (DCP_KEY_SEL_0): Select [127:0] from snvs/ocotp key as dcp key

1 (DCP_KEY_SEL_1): Select [255:128] from snvs/ocotp key as dcp key

OCRAM_STATUS

This field shows the OCRAM pipeline settings status, controlled by OCRAM_CTL bits respectively

0 (OCRAM_STATUS_0): read data pipeline configuration valid

1 (OCRAM_STATUS_1): read data pipeline control bit changed

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